module IR(
    input clk,
    input data_in_en,
    input data_out_en,
    inout [15:0] data_bus,
    input rst_n,
    (*MAX_FANOUT=10*)output reg[15:0] IR_reg//output to CU作为输入
    );
    (*MAX_FANOUT=10*)reg [15:0] data_reg;
    always @(posedge clk ) begin
        IR_reg<=data_reg;
        if (rst_n == 1'b0) begin
            data_reg <= 16'h0000;
        end
        else if (data_in_en) begin
            data_reg <= data_bus;
        end
    end
    assign data_bus = data_out_en ? data_reg : 16'hzzzz;
    
    // assign data_2_CU = data_reg;
endmodule